1. Technical Field
The present invention relates in general to display memory subsystems, graphics and display adapter systems and subsystems, and in particular to semiconductor memory devices. Still more particularly, the present invention relates to Video-RAMs and other similar memory devices.
2. Description of the Related Art
A Video-RAM (VRAM) is a 2 port RAM (Random Access Memory), which is essentially a conventional DRAM with the addition of a second port where memory data can be accessed serially. A VRAM comprises a RAM array, a Serial Access Memory (SAM) array, address/control logic, and transfer gates. The RAM array is connected to the primary (RAM) port of the VRAM and behaves in a manner identical to that of a DRAM or SRAM. The SAM array, sometimes called the Shift Register, is connected to the secondary (SAM or Serial) Port of the VRAM and may be accessed serially under the control of an external asynchronous clock, the Serial Clock. The address/control logic supervises the address multiplexing on the RAM port and provides all the control and global timing function of the VRAM. The transfer gates allow memory data to pass between the RAM array and the SAM array, under the control of the address/control logic.
The benefit of a VRAM is that the two ports can be operated independently and asynchronously, except when data must be transferred between the RAM and SAM arrays. The SAM array usually has the memory capacity of one row of the RAM array, and a full row of memory data is transferred between the RAM and the SAM in a single data transfer access. The independent and asynchronous operation of the two ports finds excellent application in display memory subsystems, where the RAM port is used to update the contents of display memory, and the SAM port provides display data to be rastered onto a display such as a CRT. The RAM port would generally operated at the frequency of the update hardware (e.g., a graphics processor). The SAM port would generally be operated at a frequency dictated by the requirements of the display. Because the display data to be rastered onto the display is obtained from the SAM port, almost all the RAM port bandwidth is available for update of the contents of display memory.
In a display memory subsystem, a VRAM supplies display data at the SAM port. Since the SAM array has only the capacity of a single row of display data, it must be continually reloaded with new rows of display data during the time of a display frame. In general, each new row of display data is obtained from a row whose address is one greater than that of the previous row. The reloading of the SAM army with new rows of display data from the RAM array is achieved by performing data transfer cycles at the RAM port. The transfer of data between the RAM array and the SAM array is the only interruption to normal DRAM access cycles at the RAM port. These data transfers may be separated into two distinct types:
1. when the SAM port is inactive, with the Serial Clock stopped; PA1 2. when the SAM port is active, with the Serial Clock running.
The former is usually associated with the loading of the SAM with display data, for the next horizontal scan-line, during periods of blanking in the display frame and, since the Serial Clock is stopped, the data transfer cycle at the RAM port requires no synchronization with the Serial Clock. The latter is usually associated with periods of active video for the horizontal scan-lines of a display frame and, since the Serial Clock is running, the data transfers cycle at the RAM port requires accurate synchronization with the Serial Clock in order to maintain the required seamless flow of display data at the SAM port. The latter is often referred to as a "Real-Time Data Transfer" in the nomenclature of VRAMs, or as a "Mid-Line Reload" in the nomenclature of VRAM-based display subsystems.
In the design of a display memory subsystem, the control and timing of "Real-Time Data Transfers" represents a major problem. A "Real-Time Data Transfer" is a critically timed real-time access, requiring accurate synchronization between RAM and SAM ports. Such a critically timed real-time access requires potentially complex and high-speed circuitry for the synchronization and control of the access. Because of this, designers of VRAM-based display memory subsystems often choose to sacrifice flexibility or under-utilize display memory in order to avoid "Mid-Line Reloads" in the display data and the associated "Real-Time Data Transfers" for the VRAMs.
The conventional method of avoiding Mid-Line Reloads, used in many VRAM-based display memory subsystems, involves a number of restrictions upon how the contents of display memory are mapped on the video display screen. These restrictions are usually:
A fixed start address for the display data on the first horizontal scan line of the display frame.
An address increment, to generate the start address of each subsequent horizontal scan-line, fixed to be equal to or a binary fraction of the capacity of the SAM arrays of the VRAMs in the display memory subsystem.
A horizontal scan-line length requiring an amount of display data not greater than the capacity of the SAM arrays of the VRAMs in the display memory subsystem.
To avoid "Mid-Line Reloads" and thereby avoid "Real-Time Data Transfers," all these restrictions must be satisfied. For a general purpose graphics adapter or display controller, these restrictions can not be applied.
Another means of avoiding "Real-Time Data Transfers" is found in some modern 1 Mb VRAMs which incorporate the so-called "Split- Register" feature. These VRAMs divide the SAM array into two halves, which can be loaded independently by so-called "Split Register Data Transfers," whereby one half of the SAM is loaded while the other half is active. This feature goes a long way to alleviating the problem, but it does not make full and efficient use of the SAM array capacity and can potentially result in twice as many data transfer accesses as would be required when not using the "Split-Register" feature.
An alternative approach that has been suggested, which allows "Real-Time Data Transfers" while still maintaining the high accuracy required for the critically timed data transfer, is to maintain all timing for the transfer internal to the VRAM, rather than external via a controller. Here, the transfer is easily synchronized with the serial output stream because all transfers are automatically initiated internally by the VRAM, based on parameters pre-programmed into the VRAM and synchronized with the Serial Clock. With this approach, no external control is introduced into the timing, so the highly accurate timing required for a Real-Time Data Transfer is achieved.
However, this approach has several disadvantages. First, the VRAM design is significantly complicated to accommodate for the internally timed transfer, making it incompatible with conventional VRAM. Second, the design is inflexible because the static nature of the parameters makes reordering the serial data output during normal operation difficult. Third, the VRAM would have to provide a busy signal or wait-state to the VRAM memory controller when making an internal data transfer in order to avoid simultaneous accesses at the RAM port. Fourth, handling this busy protocol increases complexity of the video controller circuitry, particularly if multiple VRAM busy signals must be managed. Moreover, this busy handshaking protocol renders any existing video controllers unsuitable for utilization with the VRAM.
By a novel enhancement to a conventional Video Random Access Memory (VRAM) device, the disclosed invention simply and efficiently removes the requirement for potentially complex and high-speed circuitry conventionally associated with Real-Time Data Transfers used in VRAM-based memory subsystems. Furthermore, strict mapping restrictions are not imposed on the system, and efficiency of the SAM is not sacrificed. Still further, the VRAM circuit design is not overly complicated, is extremely flexible and dynamic, and does not introduce a wait-state handshaking protocol, making the design completely compatible with existing video controllers, and a natural extension of conventional VRAM data transfers.